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PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
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DTSTART:20131121T180000Z
DTEND:20131121T183000Z
LOCATION:405/406/407
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: The power target for exascale supercomputing is 20MW, with about 30% budgeted for the memory subsystem. Commodity DRAMs will not satisfy this requirement. Additionally, the large number of memory chips (>10M) required will result in crippling failure rates. Although specialized DRAM memories have been reorganized to reduce power through 3D-stacking or row buffer resizing, their implications on fault tolerance have not been considered. We show that addressing reliability and energy is a co-optimization problem involving tradeoffs between error correction cost, access energy and refresh power; reducing the physical page size to decrease access energy increases the energy/area overhead of error resilience. Additionally, power can be reduced by optimizing bitline lengths. The proposed 3D-stacked memory uses a page size of 4kb and consumes 5.1pJ/bit based on simulations with NEK5000 benchmarks. Scaling to 100PB, the memory consumes 4.7MW at 100PB/s which, while well within the total power budget (20MW), is also error-resilient.
SUMMARY:Exploring DRAM Organizations for Energy-Efficient and Resilient Exascale Memories
PRIORITY:3
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