SCHEDULE: NOV 16-22, 2013
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Practical Nonvolatile Multilevel-Cell Phase Change Memory
SESSION: Memory Hierarchy
EVENT TYPE: Papers
TIME: 2:30PM - 3:00PM
SESSION CHAIR: Mark Gardner
AUTHOR(S):Doe Hyun Yoon, Jichuan Chang, Robert S. Schreiber, Norman P. Jouppi
ROOM:405/406/407
ABSTRACT:
Multilevel-cell (MLC) phase change memory (PCM) may provide both high capacity main memory and faster-than-Flash persistent storage. But slow growth in cell resistance with time, resistance drift, can cause transient errors in MLC-PCM. Drift errors increase with time, and prior work suggests refresh before the cell loses data. The need for refresh makes MLC-PCM volatile, taking away a key advantage. Based on the observation that most drift errors occur in a particular state in four-level-cell PCM, we propose to change from four levels to three levels, eliminating the most vulnerable state. This simple change lowers cell drift error rates by many orders of magnitude: three-level-cell PCM can retain data without power for more than ten years. With optimized encoding/decoding and a wearout tolerance mechanism, we can narrow the capacity gap between three-level and four-level cells. These techniques together enable low-cost, high-performance, genuinely nonvolatile MLC-PCM.
Chair/Author Details:
Mark Gardner (Chair) - Virginia Tech
Doe Hyun Yoon - IBM Thomas J. Watson Research Center
Jichuan Chang - Hewlett-Packard
Robert S. Schreiber - Hewlett-Packard
Norman P. Jouppi - Hewlett-Packard
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The full paper can be found in the ACM Digital Library